IHW: So what was the exact name? Llano, if we understand correctly?

Samuel Naffziger: Yes, it's Llano, with double "L". It is the codename for our first APU (accelerated processing unit), which is the description they're using for our first products that integrate CPU and GPU on a single piece of silicon. It's actually four CPU cores on the first APU product. Here we talk about new era of processor performance, and the message here is at the same time complex and very simple. If you look at the history of architectures, specificaly CPU going back to the single core, and how advancements were made to performance, it was very much driven by frequency increase. Over time that has come less and less effective as power became more of a concern. Then we moved into a multi core era which is live and kicking today and is pretty much the central AMD CPU strategy, but even then it is increasingly requiering additional processing performance to handle some of the more popular applications which are more consuming. Even business suites use more and more graphical type of applications in their busineses. That's kind of the very simplistic high level of view of how we landed on direction which we took with Llano and APUs, and how we bring in the more paralel type of processing alongside the CPU to handle also something that is not strictly dedicated to graphics, where programmers can use the paralel architecture for more traditional CPU sequential tasks.

IHW: Ok, so what about the power consumption? As we can see from the promotional slides, power consumption is 2.5 and 25 W, it's a quite difference between minimum and maximum and also it's quite low comparing to CPUs that are in use right now.

SN: For one, the 32nm technology provides power efficiency which helps drive the power consumption down, and this is a mobile focus design, so we enthisise low voltage operation. As you may know these voltages are one of the most efficienly in terms of improving the performance per wat. The other thing is this is the CPU core power consumption, it's not the entire APU. And the range of usage of this APU core is extremely broad, so it's the key feature providing great response time, good consumer experience when the performance is needed, and when it's not needed, it can deliver the good battery life.

IHW: For example, right now the HD 5000 series, their best is about 2.2 billions of transistors per chip. It's much much more than 35 milions of transistors in Llano core, so can you share with us exactly what number of transistors will the end core have?

SN: We're not disclosing details of the chip level right now.

IHW: You are aware that Intel already introduced the CPU and the GPU on the same socket, and they managed to put two different manufacturing processes in the same package. Do you care to explain what is the difference in your aproach and their aproach?

SN: What we're doing here is very different than Intel's aproach. They're trying the Larabee path and and essentialy they're validating our approach, but what they have done is just a low-end integrated graphics processor slapped in a multi chip module. That's very different of what we're doing with the Llano APU where we are taking industru leading graphics technology and fully integrating it with the CPU. Our solution shares the same memory subsystem and the integrated bus, which have significant advantages over just a low-end IGP attached in the CPU module.